Naoki Ookuma - Western Digital, Milpitas, CA

基本信息

Career Trajectory

Bio

Naoki Ookuma was born in Saitama, Japan, in 1982. He received the B.S. degree in electrical and electronic engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 2006. In 2006, he joined NEC Electronics as a Circuit Design Engineer of embedded DRAM. In 2010, he joined Western Digital, Japan (then, SanDisk Ltd., Japan) and works on the design of nand flash memory as a Technologist.

Research Interests

Papers共 11 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

30.4 A 1tb 3b/cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology

Tsutomu Higuchi,Takuyo Kodama,Koji Kato,Ryo Fukuda,Naoya Tokiwa,Mitsuhiro Abe,Teruo Takagiwa,Yuki Shimizu,Junji Musha,Katsuaki Sakurai,Jumpei Sato,Tetsuaki Utsumi,Kazuhide Yoneya,Yasuhiro Suematsu,Toshifumi Hashimoto,Takeshi Hioka,Kosuke Yanagidaira,Masatsugu Kojima,Junya Matsuno,Kei Shiraishi,Kensuke Yamamoto,Shintaro Hayashi,Tomoharu Hashiguchi,Kazuko Inuzuka,Akio Sugahara,Mitsuaki Honma,Keiji Tsunoda,Kazumasa Yamamoto,Takahiro Sugimoto,Tomofumi Fujimura,Mizuki Kaneko,Hiroki Date,Osamu Kobayashi,Takatoshi Minamoto,Ryoichi Tachibana,Itaru Yamaguchi,Juan Lee,Venky Ramachandra,Srinivas Rajendra,Tianyu Tang,Siddhesh Darne,Jiwang Lee,Jason Li,Toru Miwa,Ryuji Yamashita,Hiroshi Sugawara,Naoki Ookuma,Masahiro Kano,Hiroyuki Mizukoshi,Yuki Kuniyoshi,Mitsuyuki Watanabe,Kei Akiyama,Hirotoshi Mori,Akira Arimizu,Yoshito Katano,Masakazu Ehama,Hiroshi Maejima,Koji Hosono,Masahiro Yoshihara

2021 IEEE International Solid-State Circuits Conference (ISSCC)（2021）

Cited21Views0EIWOSBibtex

A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology

2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) (2019): 218-+

Cited45Views0Bibtex

13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology

2019 IEEE International Solid- State Circuits Conference - (ISSCC)（2019）

Cited69Views0EIWOSBibtex

11.1 A 512gb 3b/cell Flash Memory on 64-Word-line-layer BiCS Technology

ISSCC（2017）

Cited67Views0EIWOSBibtex

A 512gb 3b/Cell Flash Memory On 64-Word-Line-Layer Bics Technology

2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)pp.196-196, (2017)

Cited0Views0Bibtex

LXIVワード線層BiCS技術に関する11.1 512Gb3b/セルのフラッシュメモリ【Powered by NICT】

IEEE Conference Proceedings (2017): 197

Cited0Views0Bibtex

A 19nm 112.8mm2 64gb Multi-Level Flash Memory with 400mb/s/pin 1.8V Toggle Mode Interface

N. Shibata, K. Kanda,T. Hisada, K. Isobe, M. Sato, Y. Shimizu, T. Shimizu, T. Sugimoto, T. Kobayashi,K. Inuzuka,N. Kanagawa, Y. Kajitani, T. Ogawa,J. Nakai,K. Iwasa, M. Kojima,T. Suzuki, Y. Suzuki, S. Sakai, T. Fujimura, Y. Utsunomiya, T. Hashimoto,M. Miakashi, N. Kobayashi, M. Inagaki, Y. Matsumoto, S. Inoue, D. He, Y. Honda,J. Musha, M. Nakagawa, M. Honma, N. Abiko,M. Koyanagi,M. Yoshihara,K. Ino, M. Noguchi, T. Kamei, Y. Kato, S. Zaitsu,H. Nasu,T. Ariki,H. Chibvongodze, M. Watanabe, H. Ding,N. Ookuma,R. Yamashita,G. Liang,G. Hemink, F. Moogat,C. Trinh,M. Higashitani, T. Pham,K. Kanazawa

2012 IEEE International Solid-State Circuits Conference (2012)

Cited5Views0Bibtex

Author Statistics

Co-Author

Co-Institution

D-Core

合作者
学生
导师

No result temporarily, you can search similar Scholar with the same research interest

Data Disclaimer

The page data are from open Internet sources, cooperative publishers and automatic analysis results through AI technology. We do not make any commitments and guarantees for the validity, accuracy, correctness, reliability, completeness and timeliness of the page data. If you have any questions, please contact us by email: report@aminer.cn