Noboru Shibata - KIOXIA | 人才画像

基本信息

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职业迁徙

个人简介

Noboru Shibata received the B.E. and M.E. degrees in electrical engineering from the Tokyo University of Science, Tokyo, Japan, in 1991 and 1993, respectively. In 1993, he joined the Memory Design Department, Toshiba Corporation, Yokohama, Japan. Since 1997, he has been engaged in the research and circuit design of nand flash memories, where he has successfully developed MLC, TLC, and QLC flash memory technologies. Since 2012, he has been working on the research and development of the 3-D flash memory, such as BiCS flash and 3-D-QLC products.

研究兴趣

论文共 106 篇作者统计合作学者相似作者

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Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory

Noboru Shibata,Hironori Uchikawa,Taira Shibuya, Hirofumi Inoue

2024 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW (2024)

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Fast Readable Multi-Cell Coding for Flash Memory

Hironori Uchikawa,Noboru Shibata,Taira Shibuya

International Symposium on Information Theorypp.1149-1154, (2024)

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7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology

Noboru Shibata,Hironori Uchikawa,Taira Shibuya,Kenri Nakai,Kosuke Yanagidaira, Hirofumi Inoue

2023 IEEE International Memory Workshop (IMW)pp.1-4, (2023)

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A 1-Tb 4b/cell 4-Plane 162-Layer 3D Flash Memory with a 2.4-Gb/s I/O Speed Interface

2022 IEEE International Solid- State Circuits Conference (ISSCC)（2022）

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A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology

Noboru Shibata, Kazushige Kanda, Takahiro Shimizu, Jun Nakai, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano, Takahisa Kawabe, Taira Shibuya, Mario Sako,Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date,Manabu Sato, Tomoki Nakagawa, Junji Musha, Takatoshi Minamoto, Mizuki Uda,Dai Nakamura,Katsuaki Sakurai,Takahiro Yamashita, Jieyun Zhou,Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto,Masatsugu Ogawa, Yusuke Ochi, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto,Jumpei Sato, Namasivayam Raghunathan, Yee Lih Koh, Shuo Chen,Juan Lee, Hiroaki Nasu,Hiroshi Sugawara, Koji Hosono, Toshiki Hisada,Hiroshi Nakamura

IEEE journal of solid-state circuits（2020）

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A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology