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论文共 16 篇作者统计合作学者相似作者

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A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Koo Il Seo,Balasubramanian S Haran, Deepika Gupta,Di Guo,T Standaert,R Xie,Huiling Shang,Emre Alptekin, D I Bae,Gihyun Bae,Carol A Boye,Hong Cai,D Chanemougame, Roger Chao,Kwangting Cheng,Jeonwook Cho,Kwonhue Choi,Bassem Hamieh, J G Hong,Terence B Hook, L Jang, Jinyong Jung, R Jung, Daewoo Lee,B Lherron,R Kambhampati,Bumki Kim,Heonhwan Kim,Kunsu Kim,Tae Seon Kim,Seokbum Ko,Fee Li Lie, Deming Liu,H Mallela,Edward J Mclellan, Sharad Mehta,Pietro Montanini,Marta Mottura, J Nam, Seokho Nam, Frederick Nelson,Injo Ok, Changjoon Park, Yuseop Park,A Paul,C Prindle,Ravi P Ramachandran,Muthumanickam Sankarapandian,Viraj Y Sardesai,Andreas Scholze,S C Seo,J K Shearer,R G Southwick,Raghavasimhan Sreenivasan, S Stieg,Jay W Strane,Xinghua Sun,Moon Gyu Sung,Charan Veera Venkata Satya Surisetty,Gen Tsutsui,Nagesh K Tripathi,Reinaldo A Vega,Christopher Waskiewicz,M Weybright,C C Yeh,H Bu, Steven M Burns, D Canaperi,Mehmet Ali Celik,Matthew E Colburn,Hemanth Jagannathan, S Kanakasabaphthy,W Kleemeier,Lars W Liebmann,D Mcherron,P Oldiges,Vamsi Paruchuri,T Spooner,J H Stathis,R Divakaruni, T R Gow,John Iacoponi, J S Jenq,R Sampson,Manish Khare

VLSI Technology（2014）

引用56浏览0EIWOS引用

10Nm FINFET Technology for Low Power and High Performance Applications

D. Guo,H. Shang,K. Seo, B. Haran,T. Standaert,D. Gupta,E. Alptekin,D. Bae,G. Bae,D. Chanemougame,K. Cheng,J. Cho,B. Hamieh,J. Hong,T. Hook, J. Jung,R. Kambhampati,B. Kim,H. Kim,K. Kim,T. Kim,D. Liu,H. Mallela,P. Montanini,M. Mottura, S. Nam, L. Ok,Y. Park, A. Paul,C. Prindle, R. Ramachandran,V. Sardesai, A. Scholze,S. Seo,R. Southwick,J. Strane, X. Sun,G. Tsutsui,N. Tripathi,R. Vega,M. Weybright, R. Xie,C. Yeh,H. Bu,S. Burns,D. Canaperi,M. Celik,M. Colburn,H. Jagannathan, S. Kanakasabaphthy,W. Kleemeier,L. Liebmann,D. Mcherron,P. Oldiges,V. Paruchuri, T. Spooner,J. Stathis,R. Divakaruni, T. Gow, J. Jacoponi, J. Jenq,R. Sampson, W. Yang,M. Khare

IEEE International Conference on Solid-State and Integrated Circuit Technologypp.1-4, (2014)

引用4浏览0EIWOS引用

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\Kappa$/metal-Gate Nfinfets for High-Performance Logic Applications

Kingsuk Maitra,Ali Khakifirooz,Pranita Kulkarni,Veeraraghavan S. Basker,Jonathan Faltermeier,Hemanth Jagannathan,Hemant Adhikari,Chun-Chen Yeh,Nancy R. Klymko,Katherine Saenger,Theodorus Standaert,Robert J. Miller,Bruce Doris,Vamsi K. Paruchuri,Dale McHerron, James O'Neil, Effendi Leobundung,Huiming Bu

IEEE electron device letters（2011）

引用36浏览0EIWOS引用

Extremely-Thin SOI for Mainstream CMOS: Challenges and Opportunities

Ali Khakifirooz,Kangguo Cheng,Arvind Kumar,Pranita Kulkarni,Shom Ponoth, Balasubramanian S. Haran,Sanjay Mehta,Jin Cai, A. Byrant,J. Kuss,Lisa F. Edge,Hemanth Jagannathan,Zhibin Ren,Thomas N. Adam,Hong He,A. Kimball,Sivananda K. Kanakasabapathy, S. Schmiz,Steven J. Holmes,A. Majumdar, B. Jagannathan, D. Yang,A. Upham,Soon-Cheon Seo,J. L. Herman,Richard Johnson,Yu Zhu,P. Jamison,Zhengmao Zhu, L. H. Vanamurth,Johnathan E. Faltermeier,S. Fan,D. Horak,Terence B. Hook,Vijay Narayanan,Vamsi Paruchuri,Huiming Bu,Devendra K. Sadana, P. Kozlowsk,Bruce B. Doris,D. McHerron,Wilfried Haensch,M. Khare, E. Leobondung,J. O'Neil,Ghavam G. Shahidi

The Japan Society of Applied Physics（2010）

引用0浏览0引用

A 0.063 Mu M(2) Finfet Sram Cell Demonstration With Conventional Lithography Using A Novel Integration Scheme With Aggressively Scaled Fin And Gate Pitch

V. S. Basker,T. Standaert, H. Kawasaki,C. -C. Yeh,K. Maitra,T. Yamashita,J. Faltermeier, H. Adhikari,H. Jagannathan,J. Wang,H. Sunamura,S. Kanakasabapathy,S. Schmitz, J. Cummings,A. Inada,C. -H. Lin,P. Kulkarni, Y. Zhu,J. Kuss, T. Yamamoto,A. Kumar,J. Wahl,A. Yagishita,L. F. Edge,R. H. Kim, E. Mclellan, S. J. Holmes, R. C. Johnson,T. Levin,J. Demarest,M. Hane,M. Takayanagi,M. Colburn,V. K. Paruchuri, R. J. Miller,H. Bu,B. Doris,D. Mcherron,E. Leobandung,J. O'Neill

2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS (2010)

引用81浏览0引用

A 0.063 µm<sup>2</sup> FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

V. S. Basker,T. Standaert, H. Kawasaki,C.-C. Yeh,K. Maitra,T. Yamashita,J. Faltermeier, H. Adhikari,H. Jagannathan,J. Wang,H. Sunamura,S. Kanakasabapathy,S. Schmitz, J. Cummings,A. Inada,C. -H. Lin,P. Kulkarni, Y. Zhu,J. Kuss, T. Yamamoto,A. Kumar,J. Wahl,A. Yagishita,L. F. Edge,R. H. Kim, E. Mclellan, S. J. Holmes, R. C. Johnson,T. Levin,J. Demarest,M. Hane,M. Takayanagi,M. Colburn,V. K. Paruchuri, R. J. Miller,H. Bu,B. Doris,D. McHerron,E. Leobandung,J. O'Neill

2010 Symposium on VLSI Technology (2010)

引用0浏览0引用

Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-chip Applications

K. Cheng,A. Khakifirooz,P. Kulkarni,S. Ponoth,J. Kuss,D. Shahrjerdi,L. F. Edge,A. Kimball,S. Kanakasabapathy,K. Xiu,S. Schmitz,A. Reznicek, T. Adam,H. He,N. Loubet,S. Holmes, S. Mehta, D. Yang,A. Upham,S. -C. Seo,J. L. Herman,R. Johnson,Y. Zhu,P. Jamison, B. S. Haran,Z. Zhu, L. H. Vanamurth,S. Fan,D. Horak,H. Bu,P. J. Oldiges,D. K. Sadana,P. Kozlowski,D. McHerron,J. O'Neill,B. Doris

2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING（2009）

引用170浏览0EIWOS引用

170

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Haruhisa Kawasaki,Veeraraghavan S Basker,Takahiko Yamashita,Chang Hong Lin, Yunhui Zhu,Johnathan E Faltermeier,Stefan Antonius Schmitz, Jeffrey L Cummings,S Kanakasabapathy,Hemant Adhikari,Hemanth Jagannathan,Arun Kumar,K Maitra, June Wang,C C Yeh,Congyi Wang,Marwan H Khater,Michael A Guillorn,Nicholas C Fuller, Junbiao Chang, Liwen Chang,Ramachandran Muralidhar,Akira Yagishita, Richard J Miller,Q Ouyang, Yudong Zhang,Vamsi Paruchuri,H Bu,Bruce B Doris,Mariko Takayanagi,Wilfried Haensch,D Mcherron,J Oneill,Kazunari Ishimaru

Electron Devices Meeting（2009）

引用183浏览0EIWOS引用

183

A SiCOHBEOL interconnect technology for high density and high performance 65 nm CMOS applications

M Angyal,J Gill,M Inohara, MF Ng,SH Rhee,S Lane, H Hichri,C Penny,I Melville,V Ramachandran,BC Zhang,YK Siew,F Zhang,KC Park, KW Lee,E Kaltalioglu,SO Kim,G Matusiewicz,YH Lin, K Urata,K Kumar, J Linville,M Minami, H Maynard,M Hoinkis,T Bolom, F Feustel, KS Lam,K Inoue,A Simon, J Smith, B Baker-O'Neal,L Economikos, P Ong, Y Ishikawa, M Naujok,A Sakamoto, T Ema, G Lembach, M Kelling, T Bailey, S Marrokey,WK Li,C Christiansen,BZ Li,T Lee, F Chen,K Chanda,R Filippi, PV McLaughlin,J Demarest,D Dunn,P Flaitz,B Rhoads, C Manya, A Calabrese,P Roper, K Petrarca,W Cote,D McHerron,A Cowley,T Ivers

Advanced Metallization Conference 2005 (AMC 2005)pp.39-46, (2006)

引用0浏览0引用

ADVANCED METALLIZATION CONFERENCE 2005 (AMC 2005)pp.89-95, (2006)

引用0浏览0引用

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