Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control

Amorphous InGaZnO thin film transistors (a-IGZO TFTs) have been investigated for their applications in display panels and sensors. These IGZO TFTs are BEOL compatible and can be stacked for 3D integration making them attractive for logic and memory including neuromorphic computing applications [1-3]. For different target applications, the device performance can be varied by appropriate stack engineering. Defects in the IGZO layer strongly impact the device performance and operating regimes. Therefore, defect control is fundamental in tailoring the performance to meet the target specifications. Hydrogen and oxygen vacancies act as shallow donors in IGZO [4] . The presence of hydrogen in the processing steps contributes to the hydrogen doping. The contact metal scavenges oxygen from IGZO, resulting in oxygen vacancies. Thus, the doping in these devices is sensitive to the stack as well as the processing. In this work, we discuss different architectures, stack engineering, and device design guidelines for performance boost based on defect control.