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Roberto Nonis (Member, IEEE) was born in Udine, Italy, in 1977. He received the M.S. and Ph.D. degrees from the University of Udine, Udine, in 2002 and 2007, respectively, with a focus on modeling and design of integrated circuits for frequency synthesis. From 2006 to 2007, he held a post-doctoral position at Agere Systems Inc., Allentown, PA, USA, where he was involved in the design of high-speed and low-power dynamic comparators for ADCs. In 2007, he joined Clock and Interfaces Systems Group, Infineon Technologies AG, Villach, Austria, as an Analog-Mixed Signal Designer. He currently leads AMS Design Department, where he involved on covering clocking, high-speed interfaces, data converters, and RF AFEs. He has been a TPC Member of the International Solid-State Circuits Conference from 2015 to 2018.
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IEEE Transactions on Very Large Scale Integration (VLSI) Systemsno. 5 (2023): 636-643
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