My drive for innovation has resulted in 90+ patents, 70+ technical papers, and one book. I lead global cross-functional teams in the pursuit of continued power-performance-area-cost (PPAC) scaling. My expertise is in: Design-Technology Co-Optimization (DTCO) | Pathfinding process design kits (PDK) | Resolution enhancement techniques (RET) | Power performance area cost (PPAC) | Multiple patterning technology (MPT) | CMOS logic cell architecture definition