His work focuses on power efficiency in high-performance systems – spanning the development of new technology elements, the design of high-performance memory and power management circuits, and the exploration of novel accelerator and memory system architectures. Key contributions have included early demonstration of the FinFET structure for CMOS scaling, 8T-SRAM for voltage scaling in high-performance caches, high-speed register files with double-pumped access ports, and high-efficiency voltage conversion circuits using new passive device technologies. He is the author of 74 technical articles and 84 patents and is currently a member of the ISSCC technical program committee.