Tsai C M - Portland Technology Development, Intel Corporation

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Transistor Reliability Characterization and Comparisons for a 14 Nm Tri-Gate Technology Optimized for System-on-Chip and Foundry Platforms

C. Prasad, K. W. Park,M. Chahal,I. Meric,S. R. Novak,S. Ramey,P. Bai,H.-Y. Chang,N. L. Dias,W. M. Hafez,C.-H. Jan, N. Nidhi, R. W. Olac-vaw,R. Ramaswamy,C. Tsai

2016 IEEE International Reliability Physics Symposium (IRPS)（2016）

引用16浏览0EIWOS引用

A 14 Nm SoC Platform Technology Featuring 2nd Generation Tri-Gate Transistors, 70 Nm Gate Pitch, 52 Nm Metal Pitch, and 0.0499 Um2 SRAM Cells, Optimized for Low Power, High Performance and High Density SoC Products

C. -H. Jan, F. Al-Amoody,H. -Y. Chang, T. Chang, Y. -W. Chen,N. Dias,W. Hafez,D. Ingerly,M. Jang,E. Karl,S. K. -Y. Shi,K. Komeyli, H. Kilambi,A. Kumar,K. Byon,C. -G. Lee,J. Lee,T. Leo,P. -C. Liu,N. Nidhi,R. Olac-Vaw, C. Petersburg,K. Phoa,C. Prasad, C. Quincy,R. Ramaswamy, T. Rana,L. Rockford, A. Subramaniam,C. Tsai,P. Vandervoorn, L. Yang,A. Zainuddin,P. Bai

2015 Symposium on VLSI Technology (VLSI Technology)（2015）

引用88浏览0EIWOS引用

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Coorg R Prasad, Li Jiang,D K Singh,M Agostinelli,C Auth,Ping Bai, T M Eiles,J Hicks,C H Jan, Khyati Mistry,Sriraam Natarajan, Ben Niu,P Packan,Daniel Pantuso,I Post,Stephen M Ramey,Adele E Schmitz,Bernhard Sell,S Suthram,Julian B Thomas,Chiayin Tsai,P Vandervoorn

Reliability Physics Symposium（2013）

引用63浏览0EIWOS引用

Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

A Rahman,Ping Bai,G Curello,J Hicks,C H Jan,Muhammad Jamil, Jongho Park,K Phoa,Md Saifur Rahman,Chiayin Tsai,B Woolery,J Y Yeh

Reliability Physics Symposium（2013）

引用16浏览0EIWOS引用

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C H Jan,Ujjwal Bhattacharya,Ruth Brain,S J Choi,G Curello,Gourab Sen Gupta,W Hafez, Mijin Jang, Miyoung Kang,K Komeyli,T Leo,N Nidhi, Liyang Pan,Joongwon Park,K Phoa,Ata Ur Rahman, C Staus,Hiroko Tashiro,C Tsai,P Vandervoorn,Lingming Yang,J Y Yeh,P Bai

Electron Devices Meeting（2012）

引用357浏览0EIWOS引用

357

The Impact Of Silicon Technology Scaling Trends And The Associated Technological Innovations On Rf Cmos Device Characteristics Are Examined

C. -H. Jan,M. Agostinelli,H. Deshpande,M. A. El-Tanani,W. Hafez,U. Jalan, L. Janbay, M. Kang,H. Lakdawala,J. Lin,Y-L Lu,S. Mudanai,J. Park,A. Rahman,J. Rizk, W. -K. Shin,K. Soumyanath, H. Tashiro,C. Tsai,P. Vandervoorn,J. -Y. Yeh,P. Bai

2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST (2010)

引用0浏览0引用

A 45nm Low Power System-On-Chip Technology With Dual Gate (Logic And I/O) High-K/Metal Gate Strained Silicon Transistors

C H Jan,Ping Bai, S Biswas,M Buehler, Zhao Ping Chen,G Curello,S Gannavaram,W Hafez, J He, John C Hicks,U Jalan,Noel D Lazo, Jialiu Lin,Nick Lindert,Christopher S Litteken, Mark E Jones,Myounggon Kang,K Komeyli,Andrey V Mezhiba,Subhendu Naskar, Susan B Olson, Jihoon Park, Robert S Parker, Ling Pei,I Post, Narayan Pradhan,Ch Durga Prasad,Martin R Prince,J Rizk,Gavin L Sacks,Hideo Tashiro, Deborah Towner,C Tsai, Yipeng Wang, Lin Yang,J Y Yeh,Jim Yip,K Mistry

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST（2008）

引用54浏览0EIWOS引用

A 65nm Cmos Soc Technology Featuring Strained Silicon Transistors For Rf Applications

I. Post, M. Akbar,G. Curello,S. Gannavaram,W. Hafez,U. Jalan,K. Komeyli,J. Lin,N. Lindert,J. Park,J. Rizk, G. Sacks,C. Tsai,D. Yeh,P. Bai,C. -H. Jan

2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2（2006）

引用37浏览0EIWOS引用

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