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responsible from technology and architecture definition and development for XR, AI, and mobile CPU chipsets incorporating near-memory/in-memory computing AI, ultra-low voltage process and design methods, and stacked memory technologies. Before rejoining Qualcomm, he previously worked at Huawei, Qualcomm, IMEC, ON Semiconductor, and Tubitak Space. During his career he had various assignments for the execution and management of mobile, graphics and automotive chipset designs from concept to volume production, process technology pathfinding, analog and digital electronic design automation, and design-technology co-optimization.
He holds more than sixty published patents in the domains of semiconductors, DTCO, 3D integration, AI, memory, low-noise and low-power design, and design/test methodologies; and he has (co)-authored over one hundred publications in scientific journals/proceedings. He is the global chair of More Moore section in International Roadmap for Devices and Systems (IRDS) defining HVM roadmap of logic and memory devices in the next 15 years with the details on the structure, electrical, and underlying process modules. He is a Workstream member of American Semiconductor Innovation Coalition (ASIC) as part of US Chips Act Program. He is a senior member of IEEE.
He holds more than sixty published patents in the domains of semiconductors, DTCO, 3D integration, AI, memory, low-noise and low-power design, and design/test methodologies; and he has (co)-authored over one hundred publications in scientific journals/proceedings. He is the global chair of More Moore section in International Roadmap for Devices and Systems (IRDS) defining HVM roadmap of logic and memory devices in the next 15 years with the details on the structure, electrical, and underlying process modules. He is a Workstream member of American Semiconductor Innovation Coalition (ASIC) as part of US Chips Act Program. He is a senior member of IEEE.
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2022 IEEE International Reliability Physics Symposium (IRPS)pp.1-7, (2022)
2021 IEEE International Roadmap for Devices and Systems Outbriefspp.01-38, (2021)
semanticscholar(2020)
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Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop (2020)
N. G. Orji,M. Badaroglu,B. M. Barnes, C. Beitia, B. D. Bunday,U. Celano,R. J. Kline,M. Neisser,Y. Obeng,A. E. Vladar
Future Generation Computer Systems (2018): 659-676
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