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Jae-Gon Lee received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1998, 2000, and 2006, respectively.
He joined the SOC Division, Samsung Electronics, Hwaseong, South Korea, in 2006, where he worked mostly on the low power management circuit design for Exynos mobile SOC powering Galaxy S series smartphones. From 2006 to 2011, he worked on multiple generations of mobile SOCs in power management unit (PMU) design. In 2012, he contributed to a mobile SOC product as a physical design lead, where he gathered the knowledge on the back-end design flow. This work was extended to his research in 2013 as a Visiting Scholar at the University of California at San Diego (UCSD), San Diego, CA, USA, where he worked on the optimization of the clock tree synthesis. From 2014 to 2015, he worked on the core architecture of the fully automated clock gating (CG), when the developed the architecture definition and some of the implementations of the work presented in this article. He joined the development of the first generation in-house neural processing unit (NPU) design of Samsung from 2016 to 2017, as a Head Architect, where he contributed to the architecture exploration and the high-level performance model. From 2018 to 2019, he finished the implementation details of the automatic CG architecture. The success of this work in mobile division led the adaptations of the same technique by all SOC product lines developed by Samsung Electronics ever since. His recent interests are voltage droop mitigation, adaptive clocking, and dynamic thermal management solutions.
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2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) (2019): 130-U1540
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mag(2014)
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GLSVLSIpp.33-38, (2014)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsno. 10 (2006): 1935-1949
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