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个人简介
Gerald Pasdast received the B.S. degree in electrical engineering from San Jose State University, San Jose, CA, USA, in 1996.
From 1996 to 1997, he was a Test and Product Engineer with Cypress Semiconductor, San Jose, CA, working on FIFO and dual port RAMs. Since 1997, he has been with Intel Corporation, Santa Clara, CA, USA, worked on various IO technologies. He is currently a Senior Principal Engineer with the Central IP Team and his area of focus has been on die-to-die (D2D) IO architecture and technology since 2010 on several proprietary PHY running on both standard package (2-D) traces as well as advanced packages including EMIB (2.5-D) and Foveros (3-D chip stacking) that have been productized on server/high performance computing (HPC), graphics, and client CPUs. Most recently, he has coauthored the Universal Chiplet Interconnect express (UCIe) spec1.0. He has over 30 granted patents with an additional 20 pending mostly in the area of D2D architecture and packaging.
Mr. Pasdast is the Interim Chair of the UCIe Consortium Form Factor and Compliance WG.
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Nature Electronicsno. 3 (2024): 244-254
IEEE Transactions on Components, Packaging and Manufacturing Technologyno. 9 (2022): 1423-1431
IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021)pp.1014-1019, (2021)
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