A 16-Gb 37-Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration
Sung-Yong Cho, Moon-Chul Choi,Jaehyeok Baek, Donggun An, Sang-Hoon Kim,Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park,Kyung-Ho Lee, Hwan-Chul Jung, Gun-Hee Cho,Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin,Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim,Un-Hak Lim, Hongjun Jin,YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn,Won Ju Sung, Yoontaek Jang,Hoyoung Song,Hyodong Ban, Tae-Hoon Park,Changsik Yoo,Tae-Young Oh, SangJoon Hwang IEEE Journal of Solid-State Circuits（2024）
关键词
Decision feedback equalizer (DFE),graphic double data rate (GDDR),high-speed memory,single ended,three-level pulse amplitude modulation (PAM3),wireline transceiver
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