Sangjoon Hwang - Samsung Electronics, Hwasung, Korea

基本信息

浏览量：1

职业迁徙

个人简介

Sang-Joon Hwang received the B.S., M.S., and Ph.D. degrees in electrical engineering from Korea University, Seoul, South Korea, in 1994, 1996, and 2008, respectively. In 1996, he joined Samsung Electronics, Hwaseong, South Korea, where he has been leading the Flash Deign Team since 2017 and the Memory Product Planning Team since 2020. Since 2021, he has been leading the DRAM Design Team as the Vice President. His current research activities are focused on next generation DRAM products.

研究兴趣

论文共 41 篇作者统计合作学者相似作者

按年份排序按引用量排序主题筛选期刊级别筛选合作者筛选合作机构筛选

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5^th-Generation 10nm DRAM Process

Ikjoon Choi,Seunghwan Hong, Kihyun Kim,Jeong-Sik Hwang, Seunghan Woo,Young-Sang Kim,Cheong-Ryong Cho,Eun-Young Lee, Hun-Jae Lee,Min-Su Jung, Hee-Yun Jung,Ju-Seong Hwang,Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim,Young-Kwan Kim,Su-Jin Park,Byung-Kyu Ho,Byong-Wook Na,Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee,Hyunsung Shin, Young-Kyu Lee,Jang-Woo Ryu,Sangwoong Shin, Sungchul Park,Daihyun Lim,Seung-Jun Bae,Young-Soo Sohn,Tae-Young Oh,SangJoon Hwang

2024 IEEE International Solid-State Circuits Conference (ISSCC) (2024): 234-236

引用0浏览0EIWOS引用

13.6 A 16gb 37gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration

Sung-Yong Cho,Moon-Chul Choi,Jaehyeok Baek,Donggun An, Sanghoon Kim,Daewoong Lee, Seongyeal Yang,Gil-Young Kang,Juseop Park,Kyungho Lee,Hwan-Chul Jung, Gun-hee Cho,ChanYong Lee,Hye-Ran Kim,Yong-Jae Shin,Hanna Park, Sangyong Lee,Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim,Unhak Lim,Hong-Jun Jin,YoungSeok Lee, Young-Tae Kim,Heonjoo Ha, Jinchan Ahn,Wonju Sung, Yoontaek Jang,Hoyoung Song,Hyodong Ban,TaeHoon Park,Tae-Young Oh,Changsik Yoo,SangJoon Hwang

IEEE International Solid-State Circuits Conferencepp.242-244, (2024)

引用0浏览0EIWOS引用

Machine Learning Investigation of High-K Metal Gate Processes for Dynamic Random Access Memory Peripheral Transistor

Namyong Kwon,Joonho Bang,Won Ju Sung, Jung Hoon Han,Dongin Lee,Ilwoo Jung, Se Guen Park,Hyodong Ban,Sangjoon Hwang,Won Yong Shin,Jinhye Bae,Dongwoo Lee

APL MATERIALSno. 2 (2024)

引用0浏览0引用

13.2 A 32gb 8.0gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5Th-Generation 10nm DRAM Process

Ikjoon Choi,Seunghwan Hong,Kihyun Kım,Jeong-Sik Hwang, Seung Han Woo,Young-Sang Kim,Cheong-Ryong Cho,Eun‐Young Lee,Hun Jae Lee,Minsu Jung,Hoeryong Jung,Ju-Seong Hwang,Junsub Yoon,Woo-Hyun Lim,Hyuk Sang Yoo, Wonki Lee,Jun‐Seok Oh,Dong-Su Lee,Jong‐Eun Lee, Jun‐Hyung Kim,Young-Kwan Kim,Sujin Park,Byung-Kyu Ho,Byong-Wook Na,Hye-In Choi, Chung-Ki Lee, Soo‐Jung Lee,Hyunsung Shin,Young‐Kyu Lee,Jang-Woo Ryu,Sangwoong Shin,Sungchul Park,Dokshin Lim,Seung-Jun Bae,Young‐Soo Sohn, Tae-Young Oh,Sangjoon Hwang

openalex（2024）

引用0浏览0引用

A 16-Gb 37-Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration

Sung-Yong Cho, Moon-Chul Choi,Jaehyeok Baek, Donggun An, Sang-Hoon Kim,Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang,Juseop Park,Kyung-Ho Lee, Hwan-Chul Jung, Gun-Hee Cho,Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin,Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim,Un-Hak Lim, Hongjun Jin,YoungSeok Lee, Young-Tae Kim,Heonjoo Ha, Jinchan Ahn,Won Ju Sung, Yoontaek Jang,Hoyoung Song,Hyodong Ban, Tae-Hoon Park,Changsik Yoo,Tae-Young Oh,SangJoon Hwang

IEEE JOURNAL OF SOLID-STATE CIRCUITS (2024)

引用0浏览0EIWOS引用

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM