A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA

This article presents a digital readout integrated circuit (DROIC) with fully ON-chip image algorithm calibration based on the pixel-level 18-bit analog-to-digital converter (ADC) for infrared focal plane array (IRFPA) applications. Such ON-chip calibrations include bad pixel compensation, nonuniformity correction, and background subtraction, which are implemented to avoid ON-chip memory storage for saving power and area. The proposed DROIC was fabricated in a standard 40-nm CMOS process, and it features a $640\times512$ array size with a 30- $\mu \text{m}$ pixel pitch. The power consumption of a single-pixel ADC is less than $0.7 \mu \text{W}$ under a supply of 1.1 V. The data rate and the dynamic range are improved and it achieved a noise equivalent differential temperature (NEDT) of 1.8 mK and a peak signal-to-noise ratio (SNR) of 90.1 dB. A test comparison exhibits that the image quality is improved significantly when the calibration is enabled. It is the highest integration level reported DROIC, with fully ON-chip calibration and image-quality enhancement algorithm.