A Digital MDLL Using Switched Biasing Technique to Reduce Low-Frequency Phase Noise
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)（2016）
关键词
Multiplying delay-locked loop,switched biasing technique,phase noise
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要