Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage

A Bravaix,Y Mamy Randriamihaja,V Huard,D Angot,X Federspiel,W Arfaoui,P Mora,Fernando Cacho,M Saliva,C Besset,S Renard,Didier Roy,E Vincent

Reliability Physics Symposium（2013）

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摘要

High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔNIT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures.

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关键词

cmos integrated circuits,mosfet,high-k dielectric thin films,hot carriers,silicon compounds,ac response behaviors,c28,cmos node,hk-mg structures,nmos transistors,pmos transistors,sion,accessible shallow-deep defects,bias temperature damage,bulk oxide traps,current driven mp interactions,current driven multiple particle interactions,equivalent gate-oxide thickness,gate-stack change,high-k metal gate,hot-carrier damage,interface layer,size 1.35 nm,size 40 nm to 28 nm,temperature activation,h-bond breaking rate,hot-carrier,multivibrational excitation,phonon mode,degradation,stress,high k metal gate,logic gates

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