Electrical and morphological assessment of via middle and backside process technology for 3D integration
Electronic Components and Technology Conference（2012）
关键词
cmos integrated circuits,assembling,ball grid arrays,integrated circuit packaging,three-dimensional integrated circuits,3d circuit,3d integration,bga,cmos node,analog functions,backside process technology,bottom die,digital functions,electrical assessment,face-to-face integration assembly,morphological assessment,size 65 nm,via middle process technology,assembly,silicon,resistance
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