A 0.43pj/bit True Random Number Generator
Solid-State Circuits Conference（2014）
关键词
CMOS logic circuits,calibration,jitter,random number generation,signal generators,CMOS technology,NIST tests,TRNG,bit rate 500 kbit/s,environment variations,jitter signal generator,logic probability,noise pre-amplification,offset calibration,power 214 nW,size 40 nm,small-area energy-efficient true random number generator,voltage 0.8 V
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要