A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
ISSCC（2011）
关键词
channel crosstalk,data training,error-detection coding,chip package,lc-pll,gddr5 sdram,size 40 nm,pcb,dram chips,clocks,phase locked loops,programmable dq ordering crosstalk equalizer,dram transmitter,printed circuits,channel equalization,pll off,injection-locked oscillator,system jitter reduction,equalisers,tri-mode clocking,adjustable clock-tracking bw,memory size 2 gbyte,data bus inversion,crosstalk,injection locked oscillator,jitter,phase lock loop
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