Yasumasa Tsukamoto

Yasumasa Tsukamoto (M’15) received the B.S., M.S., and Ph.D. degrees in applied physics from Osaka University, Osaka, Japan, in 1996, 1998, and 2001, respectively. He joined Mitsubishi Electric Corporation, Itami, Japan, and later transferred to Renesas Technology Corporation, Itami, in 2003, and Renesas Electronics Corporation, Kodaira, Japan, in 2010. He has been involved in the development of embedded SRAM design from 90- to 28-nm CMOS logic processes, particularly addressing variability issues on SRAM cells and assist circuitries. From 2008 to 2010, he was a Visiting Industrial Fellow at the University of California at Berkeley, Berkeley, CA, USA, where he was involved in the trigate SRAM cell as well as random telegraph noise and its effects on SRAM characteristics. He has authored or coauthored more than 35 technical papers. His current research interests include the dynamic stability of SRAM and related variability/reliability topics as well as the application of emerging devices [silicon on insulator (SOI) and multigate MOSFET] for future SRAM design. Dr. Tsukamoto was a recipient of the Young Researcher Award and the Best Paper Award.