Mh Cho

Min Hee Cho received the B.S. degree (summa cum laude) from Yonsei University, Seoul, South Korea, the M.S. degree from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, and the Ph.D. degree from the University of California, Berkeley, CA, USA, in 2012. He has been engaged in the research on advanced device technologies such as SOI, TFET, and capacitorless DRAM. He was a DRAM Process Integration Engineer with Samsung Electronics Company Ltd., from 2000 to 2007, where he is a Principal Engineer with the Technology Planning Team, Semiconductor Research and Development Center. He was a short course Lecturer at the 23rd the Korean Conference on Semiconductors in 2016. He was involved in the development of DRAM integration using sub-20-nm technology nodes. He was also one of the main members to develop recess channel array transistor in DRAM. He has authored or co-authored 30 papers. He holds over 27 U.S. patents and 37 Korean patents. His current research interests include the next generation DRAM and future semiconductor technologies.