Konin Koua

Konin Koua received the Engineering degree from the École Nationale Supérieure d’Ingénieurs de Caen, Caen, France, in 2007, and the M.A.Sc. degree in electrical engineering from the Université de Sherbrooke, Sherbrooke, QC, Canada, in 2010. He held internship positions at Careland Information System, Shenzhen, Guangdong, China, and the Brookhaven National Laboratory (BNL), Upton, NY, USA. Since 2010, he has been a Research Professional with the Groupe de Recherche en Appareillage Médical de Sherbrooke (GRAMS), Université de Sherbrooke, where he has been contributing and leading ASICs tape-outs on low-noise front-end electronics for positron emission tomography scanners and on neural recording and stimulation since 2017. In addition, he supports the development of new 2.5-D assembly processes at the 3IT.micro prototyping platform of the Université de Sherbrooke since 2014. In 2016, he was a Visiting Scientist with the Stanford Linear Accelerator Center (SLAC), Menlo Park, CA, USA, to contribute to ASIC design for the ATLAS experiment at CERN, Meyrin, Switzerland. Since 2014, he has been holding fixed-term consulting positions as a Layout Designer with Cadence Design Systems, Montreal, QC, Canada, where he has been still contributing to SerDes and memory interface IPs in advanced CMOS nodes (down to 5 nm) as a Layout Lead Design Engineer since 2019. His current research interests include readout electronics for radiation instrumentation, wireless neural recording and stimulation, and advanced assembly for 2.5-D/3-D integration.