Nikola Katic (Member, IEEE) received the B.Sc. degree in electrical engineering from the School of Electrical Engineering, University of Belgrade, Belgrade, Serbia, in 2008, and the M.Sc. and Ph.D. degrees in electrical and electronic engineering from the Swiss Federal Institute of Technology Lausanne (EPFL), Lausanne, Switzerland, in 2010 and 2014, respectively. He joined the Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, in 2016, where he was a Post-Doctoral Fellow until 2017. From 2014 to 2021, he also held a senior analog IC design and research and development positions at Samsung Electronics, Seoul, Korea, Synopsys Inc., Toronto, and Intel Corporation. He is currently a Director of ASIC design and development with Stathera Inc, Montreal, QC, Canada, where he works on clock generation, frequency synthesis, and overall timing solutions for the new generation of communication products. His research interests include CMOS image sensor design, analog-to-digital converters (ADCs), phase locked loops (PLLs), high-speed analog and mixed-signal integrated circuit design, and signal and image processing.