基本信息
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职业迁徙
个人简介
Interests
My main research interest is developing and applying automated formal verification techniques as a practical debugging tool for designing protocols, computer systems, software, and VLSI chips.
As the marketplace demands more features and higher performance delivered in shorter development times, traditional debugging and validation techniques are not keeping pace. Currently, large chip design projects spend more resources on validation than on design, and major projects in the future will likely require 2-3 validation engineers for each design engineer. Clearly, additional tools are needed to help debug designs.
My main research interest is developing and applying automated formal verification techniques as a practical debugging tool for designing protocols, computer systems, software, and VLSI chips.
As the marketplace demands more features and higher performance delivered in shorter development times, traditional debugging and validation techniques are not keeping pace. Currently, large chip design projects spend more resources on validation than on design, and major projects in the future will likely require 2-3 validation engineers for each design engineer. Clearly, additional tools are needed to help debug designs.
研究兴趣
论文共 123 篇作者统计合作学者相似作者
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期刊级别
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CoRR (2024): 3-23
arXiv (Cornell University) (2022)
John Backes,Sam Bayless,Byron Cook,Catherine Dodge,Andrew Gacek,Alan J. Hu,Temesghen Kahsai, Bill Kocik,Evgenii Kotelnikov,Jure Kukovec,Sean McLaughlin, Jason Reed,Neha Rungta, John Sizemore, Mark A. Stalzer, Preethi Srinivasan,Pavle Subotic,Carsten Varming, Blake Whaley
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作者统计
#Papers: 123
#Citation: 4081
H-Index: 33
G-Index: 62
Sociability: 6
Diversity: 2
Activity: 1
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