Notched gate MOSFET for capacitance reduction in RF SOI technology

Lucas Antunes,Pascal Masson,Julien Amouroux,Stephane Monfray,Julien Dura,Frederic Gianesello, Julien Babic,Romain Debroucke,Loic Welter,Siddhartha Dhar, Bernadette Gros,Clement Charbuillet,Franck Julien,Guillaume Bertrand,Arnaud Regnier, Alain Fleury

2023 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)（2023）

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摘要

Reduction of parasitic front-end capacitance is one of the key factors to improve the performance of RF applications. In this work, we report the development of an atypical gate architecture allowing the reduction of the source/drain overlap capacitances of a PD-SOI n-MOS transistor. After presenting the process flow and monitoring methods, we discuss the low frequency and RF electrical results such as C OFF , R ON , RF Vmax .

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关键词

RF SOI,Switch,Overlap capacitance,Miller capacitance,MOSFET,Notched gate,Process,Monitoring

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