A 4.1 W Quadrature Doherty Digital Power Amplifier with 33.6% Peak PAE in 28nm Bulk CMOS

5G mobile communication puts forward higher throughputs and higher output-power requirements, especially at the base station side. As shown in Fig. 25.1.1, compared to the traditional analog-transmitter architectures with high-power GaAs/GaN power-amplifier (PA) modules, digital transmitters (DTXs) align with Moore's law to provide compact system size, high system efficiency, and better interface to digital baseband, thus enabling compact and fast system integration as well as a flexible architecture for 5G massive-MIMO applications. However, due to the low supply and breakdown voltages as well as the high substrate loss of advanced CMOS technologies, the design of a high-power high-efficiency digital PA (DPA) is challenging. Besides, 5G communication systems adopt OFDM and high-order QAM modulation techniques for higher data-rates, which introduces high PAPR issues and degrades PA average efficiencies. A quadrature DTX architecture is more suitable for wideband modulation signals than the polar counterparts, but it has limited output power and efficiency due to the I/Q vector combination. To address aforementioned problems, an 8-way differential power-combined quadrature DPA with IQ-reuse and Doherty techniques is proposed in this work. The DPA achieves a 4.1W (36.1dBm) peak $\mathrm{P}_{\text{out}}$ and a 33.6% peak PAE in 28nm bulk CMOS.