Enhancing Testbench Quality via Genetic Algorithm

Generating quality testbenches during the verification of hardware designs is a highly challenging task. High quality testbenches with appropriate constraints assist in enhancing verification runs leading to quick debug. However, for the purpose of obtaining meaningful constraints in the testbench, a systematic methodology is needed. We propose Genetic Algorithm-based methodology for obtaining testbenches directed towards bug localization. The proposed methodology utilizes coverage metrics for providing feedback to the testbench enhancement process. We perform detailed case studies on two designs to evaluate the proposed methodology. Experimental results illustrate that with the generated constraints, a directed testbench can be crafted for exposing the design bug.