Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS 2 Channel Directly Grown on SiO $_{{x}}$ /Si Substrates Using Area-Selective CVD Technology

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS ₂ film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS ₂ channels on SiO _x /Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10 ⁶ , a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).