First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx /Si substrate
2019 Symposium on VLSI Technology(2019)
摘要
Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS
2
p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS
2
comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS
2
growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of ~106, a S.S. of ~97 mV/dec., and nearly zero DIBL.
更多查看译文
关键词
channel area-selective CVD growth,area-selective channel material growth,p-channel field-effect transistors,p-FETs,SiOx-Si
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要