Configurable Fast Cycle-Approximate Timing Estimation for Instruction-Level Emulators

Timing estimation, a significant process in microprocessor design, should be performed promptly and accurately by the simulators to exploit the enormous design space of processors. The challenging task is how to integrate the timing data generated by the timing models of various processor components of a functional simulator, such as pipeline, branch predictor, and cache. The timing model of one processor component must interact with the other processor components, the same way processor components interact with each other in real machines for accurate timing estimation and are individually configurable and produce timing data for fast simulation. In this article, we present a configurable, fast, and cycle-approximate timing estimation method, for instruction-level emulators to solve the timing model problem. We extend QEMU, a dynamic binary translation functional emulator, to allow timing models of different processor components to be plugged in, to provide cycle-approximate timing information, while at the same time keep the fast simulation speed by providing a Timing Record Caching technique. In the proposed model, the pipeline timing of each basic block is fixed and independent of others while maintaining the timing accuracy at the same time. We have also provided instrumentation and profiling capability to help the designers to analyze and find design bottlenecks.