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Mark Smyth received the B.E. and M.Eng.Sc. degrees in electrical engineering from the University College Cork, Cork, Ireland, in 1995 and 1998, respectively.
He held Senior Analog Design roles with Ceva Technologies, Cork, Ireland, from 1997 to 2005, Freescale, Austin, Texas, United State, from 2005 to 2007, and Irish startup Redmere,from 2007 to 2012. From 2012 to 2015, he was a Systems Architect and the Technical Lead with the Wireline Transceiver Group, Xilinx, Cork, that designed 16 Gbs Transceivers on 20 and 16 nm process nodes for Xilinx field-programmable gate array products. He is currently a Senior Researcher (analog) with MCCI, Tyndall Institute, Cork, Ireland, where he leads a design team engaged in the design of next generation circuits for high-speed communication technologies. He holds multiple U.S. patents. His current research interests include high speed clocking and SerDes transceivers.
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