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个人简介
I am a Research Associate in the Computer Architecture Group at the University of Cambridge Computer Laboratory. I completed my PhD thesis , High-performance memory safety - Optimizing the CHERI capability machine, supervised by Professor Simon More, during which I worked on compressed capabilities and efficient tagged memory. I also worked on a formal model of the CHERI MIPS extensions, written in the L3 ISA modeling language. I am currently working on an ISA modeling framework in the Bluespec System Verilog language, and implementing RVBS (pronounced "rubs"), a RISC-V model. I contribute to the TestRIG effort aiming at providing a framework to help verify RISC-V implementation using fuzz testing. I actively contribute to blarney, a Haskell library for hardware description.
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论文共 15 篇作者统计合作学者相似作者
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Alexandre Joannou,Peter Rugg,Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas,Matthew Naylor, Michael Roe,Robert N. M. Watson,Peter G. Neumann,Simon W. Moore
Franz A. Fuchs,Jonathan Woodruff,Peter Rugg, Marno Van der Mass,Alexandre Joannou,Alexander Richardson,Jessica Clarke,Nathaniel Wesley Filardo,Brooks Davis,John Baldwin,Peter G. Neumann,Simon W. Moore,
2023 IEEE 41ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCDpp.578-586, (2023)
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (2019)
semanticscholar(2018)
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ACM SIGOPS Operating Systems Reviewno. 2 (2017): 569-583
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