Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node

H. Kükner,G. Mirabelli, S. Yang, L. Verschueren,J. Bömmels, J. Y. Lin,D. Abdi,A. Farokhnejad, A. Zografos,N. Horiguchi,M. Garcia Bardon,G. Hellings,J. Ryckaert

2024 IEEE International Electron Devices Meeting (IEDM)（2024）

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Abstract

Complementary FET (CFET) device architecture with stacked n-/p-FETs is an outstanding option, promising power, performance, area scalability in the post-FinFET device era. Among several options, the double-row (DR) CFET architecture leads to reduced process complexity in the middle-of-line (MOL), and gains in logic and SRAM area, by scaling to 3.5Tracks x CPP per 2 FETs. Projections show ~40% area and ~12% power scaling potential.

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Key words

Technology Node,Design-technology Co-optimization,Complementary FET,Complex Process,Device Architecture,Double Row,Promising Power,Process Flow,Cell Height,Area Overhead

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