Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects
Symposium on VLSI Technology(2024)
Abstract
A novel metal stack scheme with a sub-nm, sandwiched TiN or W layer, a so-called defect mitigation layer (DML) between Ru is proposed and found to be less prone to lateral attack and line-break formation during direct-metal-etch (DME) of Ru semi-damascene (semi-D) lines compared to those without DML. With increasing thickness (t k ) of TiN-DML, we achieve up to 5x lower defect density and resistance (R) yield >99%, <5% 1 σ of R on AR~4-6, CD~6-11 nm, metal pitch (MP)=18-26 nm lines. The improvement is higher on AR~6 lines than AR~4 which makes DML a promising approach to enable AR≥6 semi-D interconnects. No R penalty is found with TiN-DML for the investigated line lengths> 10 μm. Thermal shock reliability test shows good quality of HAR Ru line interfaces with TiN-DML.
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Key words
CMOS area scaling,semi-damascene,defect mitigation layer (DML),direct-metal-etch (DME),ruthenium,interconnects
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