Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects

Anshul Gupta, Shreya Kundu, Stefan Decoster, K. Sah, G. Delie, B. Truijen,Davide Tierno, Giulio Marti, O. Varela Pedreira, B. Kenens, Y. Hermans, C. Adelmann,B. de Wachter, Ivan Ciofi, G. Murdoch, A. Cross,Seongho Park, Zsolt Tokei

Symposium on VLSI Technology（2024）

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Key words

CMOS area scaling,semi-damascene,defect mitigation layer (DML),direct-metal-etch (DME),ruthenium,interconnects

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