Experimental Demonstration of High Precision Time Transfer in FPGA for 5G and 6G Networks

With the current roll out of 5G and efforts to accelerate the 6G framework, network and applications are evolving to a scenario where real-time requirements will be more critical and complex than today. Time transfer and synchronization mechanisms will therefore remain as a fundamental building block of the infrastructure. In this context, this paper demonstrates an FPGA-based high precision time transfer prototype to timestamp events and synchronise two nodes in a network. In the core of a time-to-digital converter, a 2048-bits delay line provides 3.9 ps of theoretical resolution and 4.97 ps achieved on-chip. The system reaches 11.7 ps scale precision when synchronizing central and remote nodes in the best case, while holding a single-shot precision of 42.9 ps. We incorporate the idea of periodically offset correction to account for the time taken for timestamps be transmitted over an optical network with several scenarios of experimentation. To compensate for physical imperfections, calibration is post-performed in software. Our results show that the system consumes less than 5% of a high-performance FPGA, which makes the solution suitable for deployment alongside multiple low-latency hardware designs for 5G and 6G components.