Bias and Temperature Stress Effects in IGZO TFTs and the Application of Step-Stress Testing to Increase Reliability Test Throughput

Indium–gallium–zinc–oxide thin-film transistors (IGZO TFTs) are widely used in numerous applications including displays and are emerging as a promising alternative for flexible IC production due to their high transparency, superior field-effect mobility, and low-temperature processability. However, their stability under different voltage stresses remains a concern, primarily due to carrier trapping in the gate dielectric and point defect creation. This study involves the fabrication of IGZO TFTs and their subsequent bias stress testing in linear and saturation regions. The impact of a passivation layer on top of the active channel is investigated to mitigate bias stress susceptibility. The passivated thin-film transistors (TFTs) exhibit reduced bias stress susceptance, with $\Delta \textit{V}_\textit{T}$ only moderately affected by the positive gate-bias stress (PGBS). This suggests that fewer electrons are being trapped at the interface between the dielectric/semiconductor. Conventional bias stress testing methods for TFTs are time-consuming and depend on air-stable devices. To address this, we introduce a “voltage step-stress” (VSS) approach. This method offers an accelerated way to conduct bias stress measurements without compromising test accuracy, reducing testing time by 8 hours (a 45% relative reduction).