13.1 A 35.4gb/s/pin 16gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry
Jaehyeok Yang,Hyeongjun Ko,Kyunghoon Kim, Hyunsu Park,Jihwan Park,Ji-Hyo Kang,Jinyoup Cha, Seongjin Kim,Young-Taek Kim, Minsoo Park,Gangsik Lee,Keonho Lee, Sanghoon Lee, Gyunam Jeon,Sera Jeong,Yongsuk Joo,Jaehoon Cha, Steve Hwang,Boram Kim,Sangyeon Byeon, Sungkwon Lee, Hyeonyeol Park,Joohwan Cho, Jonghwan Kim openalex（2024）
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