Design Space for the Scaled Ferroelectric MirrorBit Technology for High-Density NVM Storage

We show the scaling of the FeFET-based MirrorBit, which doubles the chip storage capacity. In addition to the conventional bit, another bit is programmed by applying a non-uniform field across the ferroelectric gate. The TCAD model, calibrated with GlobalFoundries’ 28 nm bulk-HKMG CMOS technology fabricated FeFET, unravels the scalability design criteria of the ferroelectric-MirrorBit technology up to 28 nm gate length. Results show a substantial $\sim$ 48% memory window enhancement for the additional bit of the scaled device.