A Model & Design Methodology for Dead Time Linearised Current Controlled Ring Oscillator ADCs

The Current Controlled Ring Oscillator’s (CCRO) non-linear characteristic, has limited its performance in ADCs and the lack of an analytical model for this non-linearity has slowed its adoption. Previously published work has constrained CCRO non-linearity to a dead time. In this work, we present a model for understanding the dynamic performance of that linearised CCRO using its dead time. We also present a systematic CCRO design methodology to demonstrate the trade-offs required to achieve a specified performance, allowing designers to evaluate potential ADC performance before the schematic design stage. The model is validated using measured results from a CCRO-based current-domain ADC with 50dB SNDR at 1MHz NBW in 65nm CMOS.