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A 0.075-mm2 6-15.3 GHz Active Digital Step Attenuator With Novel Current-Tuning Topology for Phased-Array Radar System

Bofan Chen,Zhiqun Li,Zhiying Xia, Zhaoyu Fang, Danyu Zhou

IEEE Transactions on Circuits and Systems II: Express Briefs(2024)

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摘要
A fully integrated 6-15.3 GHz active digital step attenuator (DSA) with 5-bit digital gain control for phased-array radar system in SMIC 40-nm CMOS technology is presented in this brief. Based on a novel current-tuning variable gain amplifier (VGA)-topology, amplitude control over a wider band is achieved. The main amplification common-source (CS) transistor was designed to operate in the linear region for a larger attenuation range. The fabricated active DSA exhibits a 15.5-dB tuning range with 0.5-dB tuning step, constant input and output impedance in various attenuation states and good matching characteristics. The measured root-mean-square (RMS) amplitude and phase errors are respectively <0.3 dB and <2.95∘ over 6-15.3 GHz with a fractional bandwidth of 87.3%. The measured input 1-dB compression point (IP1dB) is ≥-1.07 dBm with power consumption of 18.4-29.6 mW from a 1.2-V supply. Since no additional phase-compensation circuit is required, the core chip only occupies 0.075 mm2 after elaborate design.
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关键词
Digital step attenuator (DSA),CMOS,phased-array radar system,current-tuning,VGA-topology
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