gm/ID methodology applied to ring oscillators

This work presents a ring oscillator design flow that calculates the transistor’s dimensions and bias currents that meet the oscillation frequency and phase noise requirements using only pre-calculated tables and MATLAB scripts. The methodology combines look-up tables, the gm/ID methodology, and the square root of the delay K. Results indicate a significant correlation between calculation and simulations with a variation percentage of the frequency oscillation from 2.3% up to 29% for oscillators designed in a TSMC 180 nm CMOS technology.