Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications

The 56Gbaud Retimer chip is the core chip for high-speed optical communication data transmission of high performance computers, and its jitter performance restricts the overall performance of optical module high performance computers. Aiming at the difficult problem of low jitter performance of traditional high-speed Retimer chips, a low jitter Retiemr circuit framework based on CDR+ PLL is proposed, using a jitter-cancelling filter circuit to improve the output data jitter performance and solving the problem of high output data jitter caused by direct sampling and forwarding of traditional Retimer. The circuit is designed using a 28nm process with an area of 0.18mm2. Simulation results show that the output data jitter of the Retimer is 741 fs when fed with 112 Gbps of high-speed PAM4 data, a 31.4% reduction compared to conventional Retimer structures.