Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking

M. Kobrinsky,J. D Silva, E. Mannebach, S. Mills,M. Abd El Qader, O. Adebayo, N. Arkali Radhakrishna,M. Beasley, J. Chawla, S. Chugh, E. Clinton,A. Dasgupta, U. Desai, E. De Re,G. Dewey, T. Edwards, C. Engel, R. Galatage,T. Ghani, V. Gudmundsson, L. Hibbeler, J. Hicks,B. Krist,R. Mehandru,I. Meric,P. Morrow, D. Nandi,D. Pantuso, P. Patel, C. Pawashe,M. Radosavljevic,R. Ramamurthy, D. Samanta, S. Cekli, L. Shoer,A. St Amour, L. H. Tan, S. Yemenicioglu, X. Wang, J. A. Wiedemer

2023 International Electron Devices Meeting (IEDM)（2023）

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摘要

The recent report of a high-yielding process with Back-Side Power Delivery (BSPD) using PowerVia, the benefits obtained on an Intel E-core implementation, and the imminent deployment of PowerVia in High- Volume Manufacturing (HVM), are driving a rapid expansion of R&D across the Si Industry to enable future deployments of this seminal innovation. One such example is the recent experimental demonstration of back-side contacts (BSCONs), which bring about performance and scaling benefits. In this paper, we will identify and discuss potential directions beyond PowerVia, and the key process advances required to enable them. Three key R&D thrusts will be discussed: (i) scaling of the BSPD, (ii) introduction of new functionality on the back-side interconnects stack beyond power delivery, and (iii) efficient device stacking.

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关键词

Power Delivery,Device Stack,Backside Power,Performance Benefits,Device Performance,Front Side,Back Side,Additive Scale,Cell Height,Interconnecting Layer

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