Experimental demonstration and modeling of a ferroelectric gate stack with a tunnel dielectric insert for NAND applications

Dipjyoti Das, Hyeonwoo Park, Zekai Wang, Chengyang Zhang,Prasanna Venkatesan Ravindran,Chinsung Park,Nashrah Afroze,Po-Kai Hsu,Mengkun Tian, Hang Chen,Winston Chern,Suhwan Lim, Kwangsoo Kim,Kijoon Kim,Wanki Kim,Daewon Ha,Shimeng Yu,Suman Datta,Asif Khan

2023 International Electron Devices Meeting (IEDM)（2023）

Cited 0|Views29

No score

Key words

Gate Stack,Ferroelectric Gate,Ferroelectric Gate Stack,Middle Layer,Total Thickness,Polarization Direction,Bias Conditions,Al2O3 Layer,Hole Trapping,Design Space Exploration,Electron Hole,Effective Screening,Charge Trapping,Flat Band,Charge Screening,Ferroelectric Layer

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined