Experimental study on ultra-thin silicon-based VC for chip-level heat dissipation

The trend towards miniaturization and integration of integrated circuits has led to the emergence of local hotspots with high heat flux and high temperature frequently. Integrating vapor chamber (VC) directly on the surface of semiconductor electronic devices, can effectively address the problem of overheating on the chip surface, and is therefore considered as a promising thermal management solution. However, the challenge of reducing the size of the VC while improving its heat transfer performance cannot be ignored. To address this, a silicon-based VC with thickness of 0.6 mm is designed and fabricated in this study. Structural optimization is carried out, including the design of three types of wicks using square micropillar arrays and two types of support columns including solid and porous and an experimental system is built to study the influence of these structures on the heat transfer performance of VC. The results indicate that the VC can still function normally under the highest heat flux of 123.6 W/cm(2), resulting in lowest thermal resistance of 1.54 degrees C/W. For wicks, the thermal resistance of VC with characteristic size of 10 mu m is reduced compared with that of 20 mu m. The introduction of gradient wick, that is, using small-size (10 mu m) micropillar arrays in heating area and big-size (20 mu m) micropillar arrays in non-heating area, can effectively reduce the thermal resistance of VC. Moreover, the solid support columns are found being advantageous in reducing the thermal resistance of VC, while porous support columns improve the surface temperature uniformity of VC. This work provides a feasible path to optimize silicon-based VC.