Workload-Aware Periodic Interconnect BIST
IEEE design & test(2023)
Abstract
System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an approach for periodic in-system testing which maintains a reliability profile to detect potential problems before they actually cause a failure. Relying on a common infrastructure for EM-aware system workload management and test, it minimizes the stress induced by the test itself and contributes to the self-healing of system-induced electromigration degradations.
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Key words
Crosstalk,Wires,Delays,Reliability,Dynamic scheduling,Stress,Degradation
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