High Performance and Energy Efficient Floating-Point Multiplier on FPGA

In this paper, a high performance and energy efficient double-precision floating-point multiplier is designed and implemented on FPGA devices. A novel mapping solution of the mantissa multiplier is proposed which makes full use of the DSP blocks and requires less pipeline stages. In addition, a dual-mode floating-point multiplier is also proposed in this paper which is designed by splitting the components of the proposed double-precision multiplier. Two parallel single-precision operations are supported. For comparison purpose, the proposed architecture is implemented on Xilinx Virtex-5 (xc5vlx155ff1760-3) device, where the proposed double-precision multiplier can run 3.4% faster than previous work with less latency and can run 32.3% faster than the IP core multiplier with same latency. The proposed dual-mode multiplier can run 20.9% faster than previous fastest dual-mode design. In terms of energy consumption, the proposed double-precision multiplier consumes 43.3% less energy per operation compared to the double-precision IP core. The proposed dual-mode multiplier can achieve 24.5% less energy per operation compared to the double-precision IP core. The implementation results of the proposed architectures on latest Xilinx Virtex-7 and Altera Arria-10 devices are provided.