A 0.99μs FFT-Based Fast-Locking, 0.82Ghz-to-4.1ghz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces
2023 IEEE Custom Integrated Circuits Conference (CICC)（2023）
关键词
0.82GHz-to-4.lGHz,0.991JS FFT-based fast-locking,achievable area efficiency,clock distribution path,digital frequency-error recovery,digital PLL,DPLL-based lnput-jitter-filtering clock driver,DRAM interfaces,fast frequency acquisition,highfrequency noise,jitter-filtering nature,LC oscillator,lock time,low-frequency oscillation,memory systems,mode switching,narrow frequency tuning range,negligible equivalent inductance,odd mode,output phase noise,parallel multicore topology,phase-locked loop,time-to-digital converter,wide FTR,wide-range mode-switching
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要