A 0.0035-mm² 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased Charge-Sharing Integrator, Alexander PFD, and 1-Tap DFE

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)（2023）

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clock and data recovery (CDR),reference-less,CMOS,charge sharing integrator,continuous-rate

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A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased Charge-Sharing Integrator, Alexander PFD, and 1-Tap DFE