An FFT Accelerator Using Deeply-coupled RISC-V Instruction Set Extension for Arbitrary Number of Points

Fast Fourier Transform (FFT) is one of the most widely used algorithms in digital signal processing (DSP). Many Internet of Things (IoT) devices include dedicated FFT hardware accelerators at the price of both extra hardware resources and power consumption. Limited by constrained resources for IoT applications at the edge, it is favorable as well as crucial to reduce such overhead as much as possible without sacrificing FFT performance. Meanwhile, open-source RISC-V microprocessors have become serious contenders to ARM or x86 alternatives, especially in IoT applications. Recent studies have shown that Application-specific Instruction-set Processors (ASIP) can achieve considerable acceleration performance with low overhead. This paper proposes a fine-grained RISC-V Instruction Set Architecture (ISA) extension scheme for efficient FFT operations with 12 new instructions, using four 16-bit multipliers and adders as computing units to minimize overhead. Our extended instructions are deeply coupled with the CPU pipeline, thus significantly reducing the hardware overhead of decoding and executing logic, and theoretically can accelerate the calculation of FFT with an arbitrary number of points. We demonstrate the proposed scheme on a Xilinx PYNQ-Z2 FPGA using the open-source RISC-V NutShell soft IP core, with data loading from either specially designed vector registers (V-mode) or RAM off-the-core (R-mode). The evaluation shows the proposed FFT acceleration scheme achieves a performance gain of 118 times in V-mode and 6.5 times in R-mode respectively, with only 16% power consumption required as compared to the vanilla NutShell RISC-V microprocessor.